Normalize line endings

3 files changed, 323 insertions, 323 deletions

diff --git a/tmk_core/protocol/iwrap/suart.S b/tmk_core/protocol/iwrap/suart.S
index 1b0290963..a873515e1 100644
--- a/tmk_core/protocol/iwrap/suart.S
+++ b/tmk_core/protocol/iwrap/suart.S
@@ -1,156 +1,156 @@
-;---------------------------------------------------------------------------;

-; Software implemented UART module                                          ;

-; (C)ChaN, 2005 (http://elm-chan.org/)                                      ;

-;---------------------------------------------------------------------------;

-; Bit rate settings:

-;

-;            1MHz  2MHz  4MHz  6MHz  8MHz  10MHz  12MHz  16MHz  20MHz

-;   2.4kbps   138     -     -     -     -      -      -      -      -

-;   4.8kbps    68   138     -     -     -      -      -      -      -

-;   9.6kbps    33    68   138   208     -      -      -      -      -

-;  19.2kbps     -    33    68   102   138    173    208      -      -

-;  38.4kbps     -     -    33    50    68     85    102    138    172

-;  57.6kbps     -     -    21    33    44     56     68     91    114

-; 115.2kbps     -     -     -     -    21     27     33     44     56

-

-.nolist

-#include <avr/io.h>

-.list

-

-#define	BPS	102 	/* Bit delay. (see above table) */

-#define	BIDIR	0	/* 0:Separated Tx/Rx, 1:Shared Tx/Rx */

-

-#define	OUT_1		sbi _SFR_IO_ADDR(SUART_OUT_PORT), SUART_OUT_BIT	/* Output 1 */

-#define	OUT_0		cbi _SFR_IO_ADDR(SUART_OUT_PORT), SUART_OUT_BIT	/* Output 0 */

-#define	SKIP_IN_1	sbis _SFR_IO_ADDR(SUART_IN_PIN), SUART_IN_BIT	/* Skip if 1 */

-#define	SKIP_IN_0	sbic _SFR_IO_ADDR(SUART_IN_PIN), SUART_IN_BIT	/* Skip if 0 */

-

-

-

-#ifdef SPM_PAGESIZE

-.macro	_LPMI	reg

-	lpm	\reg, Z+

-.endm

-.macro	_MOVW	dh,dl, sh,sl

-	movw	\dl, \sl

-.endm

-#else

-.macro	_LPMI	reg

-	lpm

-	mov	\reg, r0

-	adiw	ZL, 1

-.endm

-.macro	_MOVW	dh,dl, sh,sl

-	mov	\dl, \sl

-	mov	\dh, \sh

-.endm

-#endif

-

-

-

-;---------------------------------------------------------------------------;

-; Transmit a byte in serial format of N81

-;

-;Prototype: void xmit (uint8_t data);

-;Size: 16 words

-

-.global xmit

-.func xmit

-xmit:

-#if BIDIR

-	ldi	r23, BPS-1	;Pre-idle time for bidirectional data line

-5:	dec	r23     	;

-	brne	5b		;/

-#endif

-	in	r0, _SFR_IO_ADDR(SREG)	;Save flags

-

-	com	r24		;C = start bit

-	ldi	r25, 10		;Bit counter

-	cli			;Start critical section

-

-1:	ldi	r23, BPS-1	;----- Bit transferring loop 

-2:	dec	r23     	;Wait for a bit time

-	brne	2b		;/

-	brcs	3f		;MISO = bit to be sent

-	OUT_1			;

-3:	brcc	4f		;

-	OUT_0			;/

-4:	lsr	r24     	;Get next bit into C

-	dec	r25     	;All bits sent?

-	brne	1b	     	;  no, coutinue

-

-	out	_SFR_IO_ADDR(SREG), r0	;End of critical section

-	ret

-.endfunc

-

-

-

-;---------------------------------------------------------------------------;

-; Receive a byte

-;

-;Prototype: uint8_t rcvr (void);

-;Size: 19 words

-

-.global rcvr

-.func rcvr

-rcvr:

-	in	r0, _SFR_IO_ADDR(SREG)	;Save flags

-

-	ldi	r24, 0x80	;Receiving shift reg

-	cli			;Start critical section

-

-1:	SKIP_IN_1		;Wait for idle

-	rjmp	1b

-2:	SKIP_IN_0		;Wait for start bit

-	rjmp	2b

-	ldi	r25, BPS/2	;Wait for half bit time

-3:	dec	r25

-	brne	3b

-

-4:	ldi	r25, BPS	;----- Bit receiving loop

-5:	dec	r25     	;Wait for a bit time

-	brne	5b		;/

-	lsr	r24     	;Next bit

-	SKIP_IN_0		;Get a data bit into r24.7

-	ori	r24, 0x80

-	brcc	4b	     	;All bits received?  no, continue

-

-	out	_SFR_IO_ADDR(SREG), r0	;End of critical section

-	ret

-.endfunc

-

-

-; Not wait for start bit. This should be called after detecting start bit.

-.global recv

-.func recv

-recv:

-	in	r0, _SFR_IO_ADDR(SREG)	;Save flags

-

-	ldi	r24, 0x80	;Receiving shift reg

-	cli			;Start critical section

-

-;1:	SKIP_IN_1		;Wait for idle

-;	rjmp	1b

-;2:	SKIP_IN_0		;Wait for start bit

-;	rjmp	2b

-	ldi	r25, BPS/2	;Wait for half bit time

-3:	dec	r25

-	brne	3b

-

-4:	ldi	r25, BPS	;----- Bit receiving loop

-5:	dec	r25     	;Wait for a bit time

-	brne	5b		;/

-	lsr	r24     	;Next bit

-	SKIP_IN_0		;Get a data bit into r24.7

-	ori	r24, 0x80

-	brcc	4b	     	;All bits received?  no, continue

-

-	ldi	r25, BPS/2	;Wait for half bit time

-6:	dec	r25

-	brne	6b

-7:	SKIP_IN_1		;Wait for stop bit

-	rjmp	7b

-

-	out	_SFR_IO_ADDR(SREG), r0	;End of critical section

-	ret

-.endfunc

+;---------------------------------------------------------------------------;
+; Software implemented UART module                                          ;
+; (C)ChaN, 2005 (http://elm-chan.org/)                                      ;
+;---------------------------------------------------------------------------;
+; Bit rate settings:
+;
+;            1MHz  2MHz  4MHz  6MHz  8MHz  10MHz  12MHz  16MHz  20MHz
+;   2.4kbps   138     -     -     -     -      -      -      -      -
+;   4.8kbps    68   138     -     -     -      -      -      -      -
+;   9.6kbps    33    68   138   208     -      -      -      -      -
+;  19.2kbps     -    33    68   102   138    173    208      -      -
+;  38.4kbps     -     -    33    50    68     85    102    138    172
+;  57.6kbps     -     -    21    33    44     56     68     91    114
+; 115.2kbps     -     -     -     -    21     27     33     44     56
+
+.nolist
+#include <avr/io.h>
+.list
+
+#define	BPS	102 	/* Bit delay. (see above table) */
+#define	BIDIR	0	/* 0:Separated Tx/Rx, 1:Shared Tx/Rx */
+
+#define	OUT_1		sbi _SFR_IO_ADDR(SUART_OUT_PORT), SUART_OUT_BIT	/* Output 1 */
+#define	OUT_0		cbi _SFR_IO_ADDR(SUART_OUT_PORT), SUART_OUT_BIT	/* Output 0 */
+#define	SKIP_IN_1	sbis _SFR_IO_ADDR(SUART_IN_PIN), SUART_IN_BIT	/* Skip if 1 */
+#define	SKIP_IN_0	sbic _SFR_IO_ADDR(SUART_IN_PIN), SUART_IN_BIT	/* Skip if 0 */
+
+
+
+#ifdef SPM_PAGESIZE
+.macro	_LPMI	reg
+	lpm	\reg, Z+
+.endm
+.macro	_MOVW	dh,dl, sh,sl
+	movw	\dl, \sl
+.endm
+#else
+.macro	_LPMI	reg
+	lpm
+	mov	\reg, r0
+	adiw	ZL, 1
+.endm
+.macro	_MOVW	dh,dl, sh,sl
+	mov	\dl, \sl
+	mov	\dh, \sh
+.endm
+#endif
+
+
+
+;---------------------------------------------------------------------------;
+; Transmit a byte in serial format of N81
+;
+;Prototype: void xmit (uint8_t data);
+;Size: 16 words
+
+.global xmit
+.func xmit
+xmit:
+#if BIDIR
+	ldi	r23, BPS-1	;Pre-idle time for bidirectional data line
+5:	dec	r23     	;
+	brne	5b		;/
+#endif
+	in	r0, _SFR_IO_ADDR(SREG)	;Save flags
+
+	com	r24		;C = start bit
+	ldi	r25, 10		;Bit counter
+	cli			;Start critical section
+
+1:	ldi	r23, BPS-1	;----- Bit transferring loop 
+2:	dec	r23     	;Wait for a bit time
+	brne	2b		;/
+	brcs	3f		;MISO = bit to be sent
+	OUT_1			;
+3:	brcc	4f		;
+	OUT_0			;/
+4:	lsr	r24     	;Get next bit into C
+	dec	r25     	;All bits sent?
+	brne	1b	     	;  no, coutinue
+
+	out	_SFR_IO_ADDR(SREG), r0	;End of critical section
+	ret
+.endfunc
+
+
+
+;---------------------------------------------------------------------------;
+; Receive a byte
+;
+;Prototype: uint8_t rcvr (void);
+;Size: 19 words
+
+.global rcvr
+.func rcvr
+rcvr:
+	in	r0, _SFR_IO_ADDR(SREG)	;Save flags
+
+	ldi	r24, 0x80	;Receiving shift reg
+	cli			;Start critical section
+
+1:	SKIP_IN_1		;Wait for idle
+	rjmp	1b
+2:	SKIP_IN_0		;Wait for start bit
+	rjmp	2b
+	ldi	r25, BPS/2	;Wait for half bit time
+3:	dec	r25
+	brne	3b
+
+4:	ldi	r25, BPS	;----- Bit receiving loop
+5:	dec	r25     	;Wait for a bit time
+	brne	5b		;/
+	lsr	r24     	;Next bit
+	SKIP_IN_0		;Get a data bit into r24.7
+	ori	r24, 0x80
+	brcc	4b	     	;All bits received?  no, continue
+
+	out	_SFR_IO_ADDR(SREG), r0	;End of critical section
+	ret
+.endfunc
+
+
+; Not wait for start bit. This should be called after detecting start bit.
+.global recv
+.func recv
+recv:
+	in	r0, _SFR_IO_ADDR(SREG)	;Save flags
+
+	ldi	r24, 0x80	;Receiving shift reg
+	cli			;Start critical section
+
+;1:	SKIP_IN_1		;Wait for idle
+;	rjmp	1b
+;2:	SKIP_IN_0		;Wait for start bit
+;	rjmp	2b
+	ldi	r25, BPS/2	;Wait for half bit time
+3:	dec	r25
+	brne	3b
+
+4:	ldi	r25, BPS	;----- Bit receiving loop
+5:	dec	r25     	;Wait for a bit time
+	brne	5b		;/
+	lsr	r24     	;Next bit
+	SKIP_IN_0		;Get a data bit into r24.7
+	ori	r24, 0x80
+	brcc	4b	     	;All bits received?  no, continue
+
+	ldi	r25, BPS/2	;Wait for half bit time
+6:	dec	r25
+	brne	6b
+7:	SKIP_IN_1		;Wait for stop bit
+	rjmp	7b
+
+	out	_SFR_IO_ADDR(SREG), r0	;End of critical section
+	ret
+.endfunc
diff --git a/tmk_core/protocol/iwrap/suart.h b/tmk_core/protocol/iwrap/suart.h
index 72725b998..7d92be069 100644
--- a/tmk_core/protocol/iwrap/suart.h
+++ b/tmk_core/protocol/iwrap/suart.h
@@ -1,8 +1,8 @@
-#ifndef SUART

-#define SUART

-

-void xmit(uint8_t);

-uint8_t rcvr(void);

-uint8_t recv(void);

-

-#endif	/* SUART */

+#ifndef SUART
+#define SUART
+
+void xmit(uint8_t);
+uint8_t rcvr(void);
+uint8_t recv(void);
+
+#endif	/* SUART */
diff --git a/tmk_core/protocol/iwrap/wd.h b/tmk_core/protocol/iwrap/wd.h
index 99058f033..12395bf69 100644
--- a/tmk_core/protocol/iwrap/wd.h
+++ b/tmk_core/protocol/iwrap/wd.h
@@ -1,159 +1,159 @@
-/* This is from http://www.mtcnet.net/~henryvm/wdt/ */

-#ifndef _AVR_WD_H_

-#define _AVR_WD_H_

-

-#include <avr/io.h>

-

-/*

-Copyright (c) 2009, Curt Van Maanen

-

-Permission to use, copy, modify, and/or distribute this software for any

-purpose with or without fee is hereby granted, provided that the above

-copyright notice and this permission notice appear in all copies.

-

-THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

-WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF

-MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

-ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES

-WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN

-ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF

-OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

-

-

-include usage-

-    #include "wd.h"             //if in same directory as project

-    #include <avr/wd.h>         //if wd.h is in avr directory

-

-set watchdog modes and prescale

-

-usage-

-    WD_SET(mode,[timeout]);     //prescale always set

-

-modes-

-    WD_OFF                      disabled

-    WD_RST                      normal reset mode

-    WD_IRQ                      interrupt only mode (if supported)

-    WD_RST_IRQ                  interrupt+reset mode (if supported)

-

-timeout-

-    WDTO_15MS                   default if no timeout provided

-    WDTO_30MS

-    WDTO_60MS

-    WDTO_120MS

-    WDTO_250MS

-    WDTO_500MS

-    WDTO_1S

-    WDTO_2S

-    WDTO_4S                     (if supported)

-    WDTO_8S                     (if supported)

-

-examples-

-    WD_SET(WD_RST,WDTO_1S);     //reset mode, 1s timeout

-    WD_SET(WD_OFF);             //watchdog disabled (if not fused on)

-    WD_SET(WD_RST);             //reset mode, 15ms (default timeout)

-    WD_SET(WD_IRQ,WDTO_120MS);  //interrupt only mode, 120ms timeout

-    WD_SET(WD_RST_IRQ,WDTO_2S); //interrupt+reset mode, 2S timeout

-

-

-for enhanced watchdogs, if the watchdog is not being used WDRF should be

-cleared on every power up or reset, along with disabling the watchdog-

-    WD_DISABLE();               //clear WDRF, then turn off watchdog

-

-*/

-

-//reset registers to the same name (MCUCSR)

-#if !defined(MCUCSR)

-#define MCUCSR                  MCUSR

-#endif

-

-//watchdog registers to the same name (WDTCSR)

-#if !defined(WDTCSR)

-#define WDTCSR                  WDTCR

-#endif

-

-//if enhanced watchdog, define irq values, create disable macro

-#if defined(WDIF)

-#define WD_IRQ                  0xC0

-#define WD_RST_IRQ              0xC8

-#define WD_DISABLE()            do{                       \

-                                    MCUCSR &= ~(1<<WDRF); \

-                                    WD_SET(WD_OFF);       \

-                                }while(0)

-#endif

-

-//all watchdogs

-#define WD_RST                  8

-#define WD_OFF                  0

-

-//prescale values

-#define WDTO_15MS               0

-#define WDTO_30MS               1

-#define WDTO_60MS               2

-#define WDTO_120MS              3

-#define WDTO_250MS              4

-#define WDTO_500MS              5

-#define WDTO_1S                 6

-#define WDTO_2S                 7

-

-//prescale values for avrs with WDP3

-#if defined(WDP3)

-#define WDTO_4S                 0x20

-#define WDTO_8S                 0x21

-#endif

-

-//watchdog reset

-#define WDR()                   __asm__ __volatile__("wdr")

-

-//avr reset using watchdog

-#define WD_AVR_RESET()          do{                              \

-                                    __asm__ __volatile__("cli"); \

-                                    WD_SET_UNSAFE(WD_RST);       \

-                                    while(1);                    \

-                                }while(0)

-

-/*set the watchdog-

-1. save SREG

-2. turn off irq's

-3. reset watchdog timer

-4. enable watchdog change

-5. write watchdog value

-6. restore SREG (restoring irq status)

-*/

-#define WD_SET(val,...)                                 \

-    __asm__ __volatile__(                               \

-        "in __tmp_reg__,__SREG__"           "\n\t"      \

-        "cli"                               "\n\t"      \

-        "wdr"                               "\n\t"      \

-        "sts %[wdreg],%[wden]"              "\n\t"      \

-        "sts %[wdreg],%[wdval]"             "\n\t"      \

-        "out __SREG__,__tmp_reg__"          "\n\t"      \

-        :                                               \

-        : [wdreg] "M" (&WDTCSR),                        \

-          [wden]  "r" ((uint8_t)(0x18)),                \

-          [wdval] "r" ((uint8_t)(val|(__VA_ARGS__+0)))  \

-        : "r0"                                          \

-)

-

-/*set the watchdog when I bit in SREG known to be clear-

-1. reset watchdog timer

-2. enable watchdog change

-5. write watchdog value

-*/

-#define WD_SET_UNSAFE(val,...)                          \

-    __asm__ __volatile__(                               \

-        "wdr"                               "\n\t"      \

-        "sts %[wdreg],%[wden]"              "\n\t"      \

-        "sts %[wdreg],%[wdval]"             "\n\t"      \

-        :                                               \

-        : [wdreg] "M" (&WDTCSR),                        \

-          [wden]  "r" ((uint8_t)(0x18)),                \

-          [wdval] "r" ((uint8_t)(val|(__VA_ARGS__+0)))  \

-)

-

-

-//for compatibility with avr/wdt.h

-#define wdt_enable(val) WD_SET(WD_RST,val)

-#define wdt_disable()   WD_SET(WD_OFF)

-

-

-#endif /* _AVR_WD_H_ */

+/* This is from http://www.mtcnet.net/~henryvm/wdt/ */
+#ifndef _AVR_WD_H_
+#define _AVR_WD_H_
+
+#include <avr/io.h>
+
+/*
+Copyright (c) 2009, Curt Van Maanen
+
+Permission to use, copy, modify, and/or distribute this software for any
+purpose with or without fee is hereby granted, provided that the above
+copyright notice and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
+
+include usage-
+    #include "wd.h"             //if in same directory as project
+    #include <avr/wd.h>         //if wd.h is in avr directory
+
+set watchdog modes and prescale
+
+usage-
+    WD_SET(mode,[timeout]);     //prescale always set
+
+modes-
+    WD_OFF                      disabled
+    WD_RST                      normal reset mode
+    WD_IRQ                      interrupt only mode (if supported)
+    WD_RST_IRQ                  interrupt+reset mode (if supported)
+
+timeout-
+    WDTO_15MS                   default if no timeout provided
+    WDTO_30MS
+    WDTO_60MS
+    WDTO_120MS
+    WDTO_250MS
+    WDTO_500MS
+    WDTO_1S
+    WDTO_2S
+    WDTO_4S                     (if supported)
+    WDTO_8S                     (if supported)
+
+examples-
+    WD_SET(WD_RST,WDTO_1S);     //reset mode, 1s timeout
+    WD_SET(WD_OFF);             //watchdog disabled (if not fused on)
+    WD_SET(WD_RST);             //reset mode, 15ms (default timeout)
+    WD_SET(WD_IRQ,WDTO_120MS);  //interrupt only mode, 120ms timeout
+    WD_SET(WD_RST_IRQ,WDTO_2S); //interrupt+reset mode, 2S timeout
+
+
+for enhanced watchdogs, if the watchdog is not being used WDRF should be
+cleared on every power up or reset, along with disabling the watchdog-
+    WD_DISABLE();               //clear WDRF, then turn off watchdog
+
+*/
+
+//reset registers to the same name (MCUCSR)
+#if !defined(MCUCSR)
+#define MCUCSR                  MCUSR
+#endif
+
+//watchdog registers to the same name (WDTCSR)
+#if !defined(WDTCSR)
+#define WDTCSR                  WDTCR
+#endif
+
+//if enhanced watchdog, define irq values, create disable macro
+#if defined(WDIF)
+#define WD_IRQ                  0xC0
+#define WD_RST_IRQ              0xC8
+#define WD_DISABLE()            do{                       \
+                                    MCUCSR &= ~(1<<WDRF); \
+                                    WD_SET(WD_OFF);       \
+                                }while(0)
+#endif
+
+//all watchdogs
+#define WD_RST                  8
+#define WD_OFF                  0
+
+//prescale values
+#define WDTO_15MS               0
+#define WDTO_30MS               1
+#define WDTO_60MS               2
+#define WDTO_120MS              3
+#define WDTO_250MS              4
+#define WDTO_500MS              5
+#define WDTO_1S                 6
+#define WDTO_2S                 7
+
+//prescale values for avrs with WDP3
+#if defined(WDP3)
+#define WDTO_4S                 0x20
+#define WDTO_8S                 0x21
+#endif
+
+//watchdog reset
+#define WDR()                   __asm__ __volatile__("wdr")
+
+//avr reset using watchdog
+#define WD_AVR_RESET()          do{                              \
+                                    __asm__ __volatile__("cli"); \
+                                    WD_SET_UNSAFE(WD_RST);       \
+                                    while(1);                    \
+                                }while(0)
+
+/*set the watchdog-
+1. save SREG
+2. turn off irq's
+3. reset watchdog timer
+4. enable watchdog change
+5. write watchdog value
+6. restore SREG (restoring irq status)
+*/
+#define WD_SET(val,...)                                 \
+    __asm__ __volatile__(                               \
+        "in __tmp_reg__,__SREG__"           "\n\t"      \
+        "cli"                               "\n\t"      \
+        "wdr"                               "\n\t"      \
+        "sts %[wdreg],%[wden]"              "\n\t"      \
+        "sts %[wdreg],%[wdval]"             "\n\t"      \
+        "out __SREG__,__tmp_reg__"          "\n\t"      \
+        :                                               \
+        : [wdreg] "M" (&WDTCSR),                        \
+          [wden]  "r" ((uint8_t)(0x18)),                \
+          [wdval] "r" ((uint8_t)(val|(__VA_ARGS__+0)))  \
+        : "r0"                                          \
+)
+
+/*set the watchdog when I bit in SREG known to be clear-
+1. reset watchdog timer
+2. enable watchdog change
+5. write watchdog value
+*/
+#define WD_SET_UNSAFE(val,...)                          \
+    __asm__ __volatile__(                               \
+        "wdr"                               "\n\t"      \
+        "sts %[wdreg],%[wden]"              "\n\t"      \
+        "sts %[wdreg],%[wdval]"             "\n\t"      \
+        :                                               \
+        : [wdreg] "M" (&WDTCSR),                        \
+          [wden]  "r" ((uint8_t)(0x18)),                \
+          [wdval] "r" ((uint8_t)(val|(__VA_ARGS__+0)))  \
+)
+
+
+//for compatibility with avr/wdt.h
+#define wdt_enable(val) WD_SET(WD_RST,val)
+#define wdt_disable()   WD_SET(WD_OFF)
+
+
+#endif /* _AVR_WD_H_ */