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Diffstat (limited to 'lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tc0.h')
| -rw-r--r-- | lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tc0.h | 109 |
1 files changed, 109 insertions, 0 deletions
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tc0.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tc0.h new file mode 100644 index 000000000..7b3d2b859 --- /dev/null +++ b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tc0.h @@ -0,0 +1,109 @@ +/** + * \file + * + * \brief Instance description for TC0 + * + * Copyright (c) 2017 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51_TC0_INSTANCE_ +#define _SAMD51_TC0_INSTANCE_ + +/* ========== Register definition for TC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC0_CTRLA (0x40003800) /**< \brief (TC0) Control A */ +#define REG_TC0_CTRLBCLR (0x40003804) /**< \brief (TC0) Control B Clear */ +#define REG_TC0_CTRLBSET (0x40003805) /**< \brief (TC0) Control B Set */ +#define REG_TC0_EVCTRL (0x40003806) /**< \brief (TC0) Event Control */ +#define REG_TC0_INTENCLR (0x40003808) /**< \brief (TC0) Interrupt Enable Clear */ +#define REG_TC0_INTENSET (0x40003809) /**< \brief (TC0) Interrupt Enable Set */ +#define REG_TC0_INTFLAG (0x4000380A) /**< \brief (TC0) Interrupt Flag Status and Clear */ +#define REG_TC0_STATUS (0x4000380B) /**< \brief (TC0) Status */ +#define REG_TC0_WAVE (0x4000380C) /**< \brief (TC0) Waveform Generation Control */ +#define REG_TC0_DRVCTRL (0x4000380D) /**< \brief (TC0) Control C */ +#define REG_TC0_DBGCTRL (0x4000380F) /**< \brief (TC0) Debug Control */ +#define REG_TC0_SYNCBUSY (0x40003810) /**< \brief (TC0) Synchronization Status */ +#define REG_TC0_COUNT16_COUNT (0x40003814) /**< \brief (TC0) COUNT16 Count */ +#define REG_TC0_COUNT16_CC0 (0x4000381C) /**< \brief (TC0) COUNT16 Compare and Capture 0 */ +#define REG_TC0_COUNT16_CC1 (0x4000381E) /**< \brief (TC0) COUNT16 Compare and Capture 1 */ +#define REG_TC0_COUNT16_CCBUF0 (0x40003830) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 0 */ +#define REG_TC0_COUNT16_CCBUF1 (0x40003832) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 1 */ +#define REG_TC0_COUNT32_COUNT (0x40003814) /**< \brief (TC0) COUNT32 Count */ +#define REG_TC0_COUNT32_CC0 (0x4000381C) /**< \brief (TC0) COUNT32 Compare and Capture 0 */ +#define REG_TC0_COUNT32_CC1 (0x40003820) /**< \brief (TC0) COUNT32 Compare and Capture 1 */ +#define REG_TC0_COUNT32_CCBUF0 (0x40003830) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 0 */ +#define REG_TC0_COUNT32_CCBUF1 (0x40003834) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 1 */ +#define REG_TC0_COUNT8_COUNT (0x40003814) /**< \brief (TC0) COUNT8 Count */ +#define REG_TC0_COUNT8_PER (0x4000381B) /**< \brief (TC0) COUNT8 Period */ +#define REG_TC0_COUNT8_CC0 (0x4000381C) /**< \brief (TC0) COUNT8 Compare and Capture 0 */ +#define REG_TC0_COUNT8_CC1 (0x4000381D) /**< \brief (TC0) COUNT8 Compare and Capture 1 */ +#define REG_TC0_COUNT8_PERBUF (0x4000382F) /**< \brief (TC0) COUNT8 Period Buffer */ +#define REG_TC0_COUNT8_CCBUF0 (0x40003830) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 0 */ +#define REG_TC0_COUNT8_CCBUF1 (0x40003831) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 1 */ +#else +#define REG_TC0_CTRLA (*(RwReg *)0x40003800UL) /**< \brief (TC0) Control A */ +#define REG_TC0_CTRLBCLR (*(RwReg8 *)0x40003804UL) /**< \brief (TC0) Control B Clear */ +#define REG_TC0_CTRLBSET (*(RwReg8 *)0x40003805UL) /**< \brief (TC0) Control B Set */ +#define REG_TC0_EVCTRL (*(RwReg16*)0x40003806UL) /**< \brief (TC0) Event Control */ +#define REG_TC0_INTENCLR (*(RwReg8 *)0x40003808UL) /**< \brief (TC0) Interrupt Enable Clear */ +#define REG_TC0_INTENSET (*(RwReg8 *)0x40003809UL) /**< \brief (TC0) Interrupt Enable Set */ +#define REG_TC0_INTFLAG (*(RwReg8 *)0x4000380AUL) /**< \brief (TC0) Interrupt Flag Status and Clear */ +#define REG_TC0_STATUS (*(RwReg8 *)0x4000380BUL) /**< \brief (TC0) Status */ +#define REG_TC0_WAVE (*(RwReg8 *)0x4000380CUL) /**< \brief (TC0) Waveform Generation Control */ +#define REG_TC0_DRVCTRL (*(RwReg8 *)0x4000380DUL) /**< \brief (TC0) Control C */ +#define REG_TC0_DBGCTRL (*(RwReg8 *)0x4000380FUL) /**< \brief (TC0) Debug Control */ +#define REG_TC0_SYNCBUSY (*(RoReg *)0x40003810UL) /**< \brief (TC0) Synchronization Status */ +#define REG_TC0_COUNT16_COUNT (*(RwReg16*)0x40003814UL) /**< \brief (TC0) COUNT16 Count */ +#define REG_TC0_COUNT16_CC0 (*(RwReg16*)0x4000381CUL) /**< \brief (TC0) COUNT16 Compare and Capture 0 */ +#define REG_TC0_COUNT16_CC1 (*(RwReg16*)0x4000381EUL) /**< \brief (TC0) COUNT16 Compare and Capture 1 */ +#define REG_TC0_COUNT16_CCBUF0 (*(RwReg16*)0x40003830UL) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 0 */ +#define REG_TC0_COUNT16_CCBUF1 (*(RwReg16*)0x40003832UL) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 1 */ +#define REG_TC0_COUNT32_COUNT (*(RwReg *)0x40003814UL) /**< \brief (TC0) COUNT32 Count */ +#define REG_TC0_COUNT32_CC0 (*(RwReg *)0x4000381CUL) /**< \brief (TC0) COUNT32 Compare and Capture 0 */ +#define REG_TC0_COUNT32_CC1 (*(RwReg *)0x40003820UL) /**< \brief (TC0) COUNT32 Compare and Capture 1 */ +#define REG_TC0_COUNT32_CCBUF0 (*(RwReg *)0x40003830UL) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 0 */ +#define REG_TC0_COUNT32_CCBUF1 (*(RwReg *)0x40003834UL) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 1 */ +#define REG_TC0_COUNT8_COUNT (*(RwReg8 *)0x40003814UL) /**< \brief (TC0) COUNT8 Count */ +#define REG_TC0_COUNT8_PER (*(RwReg8 *)0x4000381BUL) /**< \brief (TC0) COUNT8 Period */ +#define REG_TC0_COUNT8_CC0 (*(RwReg8 *)0x4000381CUL) /**< \brief (TC0) COUNT8 Compare and Capture 0 */ +#define REG_TC0_COUNT8_CC1 (*(RwReg8 *)0x4000381DUL) /**< \brief (TC0) COUNT8 Compare and Capture 1 */ +#define REG_TC0_COUNT8_PERBUF (*(RwReg8 *)0x4000382FUL) /**< \brief (TC0) COUNT8 Period Buffer */ +#define REG_TC0_COUNT8_CCBUF0 (*(RwReg8 *)0x40003830UL) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 0 */ +#define REG_TC0_COUNT8_CCBUF1 (*(RwReg8 *)0x40003831UL) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TC0 peripheral ========== */ +#define TC0_CC_NUM 2 +#define TC0_DMAC_ID_MC_0 45 +#define TC0_DMAC_ID_MC_1 46 +#define TC0_DMAC_ID_MC_LSB 45 +#define TC0_DMAC_ID_MC_MSB 46 +#define TC0_DMAC_ID_MC_SIZE 2 +#define TC0_DMAC_ID_OVF 44 // Indexes of DMA Overflow trigger +#define TC0_EXT 0 // Coding of implemented extended features (keep 0 value) +#define TC0_GCLK_ID 9 // Index of Generic Clock +#define TC0_MASTER_SLAVE_MODE 1 // TC type 0 : NA, 1 : Master, 2 : Slave +#define TC0_OW_NUM 2 // Number of Output Waveforms + +#endif /* _SAMD51_TC0_INSTANCE_ */ |