From c6e533ce83d6ae4393e6cdf1f6d39ffefc790115 Mon Sep 17 00:00:00 2001 From: Jun Wako Date: Sun, 4 Jan 2015 03:27:24 +0900 Subject: infinity: Move project specific files to local --- keyboard/infinity/Makefile | 5 +- keyboard/infinity/infinity.ld | 156 ------------- keyboard/infinity/k20dx32_flash.cfg | 124 ---------- keyboard/infinity/mbed-infinity.mk | 45 ++++ keyboard/infinity/mbed-infinity/cmsis_nvic.c | 55 +++++ keyboard/infinity/mbed-infinity/infinity.ld | 156 +++++++++++++ keyboard/infinity/mbed-infinity/system_MK20D5.c | 299 ++++++++++++++++++++++++ keyboard/infinity/openocd.cfg | 13 -- keyboard/infinity/tool/k20dx32_flash.cfg | 124 ++++++++++ keyboard/infinity/tool/openocd.cfg | 13 ++ 10 files changed, 696 insertions(+), 294 deletions(-) delete mode 100644 keyboard/infinity/infinity.ld delete mode 100644 keyboard/infinity/k20dx32_flash.cfg create mode 100644 keyboard/infinity/mbed-infinity.mk create mode 100644 keyboard/infinity/mbed-infinity/cmsis_nvic.c create mode 100644 keyboard/infinity/mbed-infinity/infinity.ld create mode 100644 keyboard/infinity/mbed-infinity/system_MK20D5.c delete mode 100644 keyboard/infinity/openocd.cfg create mode 100644 keyboard/infinity/tool/k20dx32_flash.cfg create mode 100644 keyboard/infinity/tool/openocd.cfg (limited to 'keyboard') diff --git a/keyboard/infinity/Makefile b/keyboard/infinity/Makefile index ec9dc0027..e97f759df 100644 --- a/keyboard/infinity/Makefile +++ b/keyboard/infinity/Makefile @@ -24,7 +24,10 @@ INCLUDE_PATHS = -I. #MOUSEKEY_ENABLE = yes -include $(TMK_DIR)/tool/mbed/mk20d50m.mk +include mbed-infinity.mk include $(TMK_DIR)/tool/mbed/mbed.mk include $(TMK_DIR)/tool/mbed/common.mk include $(TMK_DIR)/tool/mbed/gcc.mk + +program: + dfu-util -D $(OBJDIR)/$(PROJECT).bin diff --git a/keyboard/infinity/infinity.ld b/keyboard/infinity/infinity.ld deleted file mode 100644 index decdaa26e..000000000 --- a/keyboard/infinity/infinity.ld +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Linker script for Massdrop Infinity - * Infinity has bootloader in top 4KB sector of flash and app should be placed after the area. - * - * based on mbed.org K20 ARM GCC linker script file: MK20D5.ld - */ - -MEMORY -{ - /* Infinity blootloader uses 4KB */ - FLASH (rx) : ORIGIN = 4K, LENGTH = 128K - 4K - RAM (rwx) : ORIGIN = 0x1FFFE0F8, LENGTH = 16K - 0xF8 -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * _reset_init : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - __vector_table = .; - KEEP(*(.isr_vector)) - *(.text.Reset_Handler) - *(.text.System_Init) - . = ALIGN(4); - - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - __bss_start__ = .; - *(.bss*) - *(COMMON) - __bss_end__ = .; - } > RAM - - .heap : - { - __end__ = .; - end = __end__; - *(.heap*) - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy : - { - *(.stack) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/keyboard/infinity/k20dx32_flash.cfg b/keyboard/infinity/k20dx32_flash.cfg deleted file mode 100644 index 714d9991f..000000000 --- a/keyboard/infinity/k20dx32_flash.cfg +++ /dev/null @@ -1,124 +0,0 @@ -# FreeScale Kinetis K20 devices with 32kB Flash and 8kB Local On-Chip SRAM, -# Nemuisan's Special for MK20DN32VFT5,MK20DX32VFT5,MK10DN32VFT5,MK10DX32VFT5 - - -source [find target/swj-dp.tcl] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME k20 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - if { [using_jtag] } { - set _CPUTAPID 0x4BA00477 - } { - # this is the SW-DP tap id not the jtag tap id - set _CPUTAPID 0x2BA01477 - } -} - -# Work-area is a space in RAM used for flash programming -# By default use 8kB -if { [info exists WORKAREASIZE] == 0 } { - set _WORKAREASIZE 0x2000 -} - -# Select "srst_only", Nemuisan said so! -echo "Kinetis MUST need Hardware SRST Control to Recover Secure-State!" -adapter_nsrst_delay 200 -reset_config srst_only - -swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME - -# It is important that "kinetis mdm check_security" is called for -# 'examine-end' event and not 'eximine-start'. Calling it in 'examine-start' -# causes "kinetis mdm check_security" to fail the first time openocd -# calls it when it tries to connect after the CPU has been power-cycled. -$_CHIPNAME.cpu configure -event examine-end { - kinetis mdm check_security -# Uncomment when gone into s*ck'n secured state! -# kinetis mdm mass_erase -} - -# K20 has minimun 8kB of SRAM and starts at 1FFFF000. -$_TARGETNAME configure -work-area-phys 0x1FFFF000 -work-area-size $_WORKAREASIZE -work-area-backup 0 -rtos auto - -# MK20DN32VFT5,MK20DX32VFT5,MK10DN32VFT5,MK10DX32VFT5 has 32kB of flash memory. -flash bank $_CHIPNAME.pflash kinetis 0x00000000 0x8000 0 4 $_TARGETNAME - - -proc mt_flash {IMGFILE} { - flash write_image erase $IMGFILE - reset run - halt - verify_image $IMGFILE - reset run - shutdown -} - -proc mt_flash_bin {IMGFILE OFFSET} { - flash write_image erase $IMGFILE $OFFSET bin - reset run - halt - verify_image $IMGFILE $OFFSET bin - reset run - shutdown -} - -proc mt_flash_hex {IMGFILE} { - flash write_image erase $IMGFILE 0 ihex - reset run - halt - verify_image $IMGFILE 0 ihex - reset run - shutdown -} - -proc mt_flash_srec {IMGFILE} { - flash write_image erase $IMGFILE 0 s19 - reset run - halt - verify_image $IMGFILE 0 s19 - reset run - shutdown -} - -proc mass_erase {} { - kinetis mdm mass_erase -} - -proc eraser {} { -# Verbose procedure confirmed erase routine - flash info 0 -# CAUTION! "flash erase_sector 0 0 last" goes into secure state!!! -# USE "mass_erase" command instead of -# flash erase_sector 0 0 last - mass_erase - shutdown -} - - -#debug_level 3 -# HLA doesn't have cortex_m commands -if {![using_hla]} { - # if srst is not fitted use SYSRESETREQ to - # perform a soft reset - cortex_m reset_config sysresetreq -} -adapter_khz 1000 -reset_config srst_only srst_nogate connect_assert_srst -gdb_target_description disable -init -reset init diff --git a/keyboard/infinity/mbed-infinity.mk b/keyboard/infinity/mbed-infinity.mk new file mode 100644 index 000000000..cd4434a23 --- /dev/null +++ b/keyboard/infinity/mbed-infinity.mk @@ -0,0 +1,45 @@ +# based on Makefile exported form mbed.org +# see http://mbed.org/handbook/Exporting-to-GCC-ARM-Embedded + +CPU = -mcpu=cortex-m4 -mthumb + +CC_SYMBOLS += \ + -DTARGET_K20D50M \ + -DTARGET_M4 \ + -DTARGET_CORTEX_M \ + -DTARGET_Freescale \ + -DTOOLCHAIN_GCC_ARM \ + -DTOOLCHAIN_GCC \ + -D__CORTEX_M4 \ + -DARM_MATH_CM4 \ + -D__MBED__=1 + +OBJECTS += \ + $(OBJDIR)/mbed-infinity/cmsis_nvic.o \ + $(OBJDIR)/mbed-infinity/system_MK20D5.o \ + $(OBJDIR)/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/startup_MK20D5.o \ + $(OBJDIR)/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/analogin_api.o \ + $(OBJDIR)/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/gpio_api.o \ + $(OBJDIR)/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/gpio_irq_api.o \ + $(OBJDIR)/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/i2c_api.o \ + $(OBJDIR)/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/pinmap.o \ + $(OBJDIR)/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/port_api.o \ + $(OBJDIR)/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/pwmout_api.o \ + $(OBJDIR)/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/rtc_api.o \ + $(OBJDIR)/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/serial_api.o \ + $(OBJDIR)/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/sleep.o \ + $(OBJDIR)/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/spi_api.o \ + $(OBJDIR)/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M/us_ticker.o + +INCLUDE_PATHS += \ + -Imbed \ + -I$(MBED_DIR)/libraries/mbed/targets \ + -I$(MBED_DIR)/libraries/mbed/targets/cmsis \ + -I$(MBED_DIR)/libraries/mbed/targets/cmsis/TARGET_Freescale \ + -I$(MBED_DIR)/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M \ + -I$(MBED_DIR)/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20D50M/TOOLCHAIN_GCC_ARM \ + -I$(MBED_DIR)/libraries/mbed/targets/hal \ + -I$(MBED_DIR)/libraries/mbed/targets/hal/TARGET_Freescale \ + -I$(MBED_DIR)/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D50M + +LINKER_SCRIPT = mbed-infinity/infinity.ld diff --git a/keyboard/infinity/mbed-infinity/cmsis_nvic.c b/keyboard/infinity/mbed-infinity/cmsis_nvic.c new file mode 100644 index 000000000..985c1d33f --- /dev/null +++ b/keyboard/infinity/mbed-infinity/cmsis_nvic.c @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2011 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "cmsis_nvic.h" + +#define NVIC_RAM_VECTOR_ADDRESS (0x1FFFE000) // Vectors positioned at start of RAM +#define NVIC_FLASH_VECTOR_ADDRESS (0x1000) // Initial vector position in flash + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { + uint32_t *vectors = (uint32_t*)SCB->VTOR; + uint32_t i; + + // Copy and switch to dynamic vectors if the first time called + if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) { + uint32_t *old_vectors = vectors; + vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; + for (i=0; iVTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS; + } + vectors[IRQn + 16] = vector; +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) { + uint32_t *vectors = (uint32_t*)SCB->VTOR; + return vectors[IRQn + 16]; +} diff --git a/keyboard/infinity/mbed-infinity/infinity.ld b/keyboard/infinity/mbed-infinity/infinity.ld new file mode 100644 index 000000000..decdaa26e --- /dev/null +++ b/keyboard/infinity/mbed-infinity/infinity.ld @@ -0,0 +1,156 @@ +/* + * Linker script for Massdrop Infinity + * Infinity has bootloader in top 4KB sector of flash and app should be placed after the area. + * + * based on mbed.org K20 ARM GCC linker script file: MK20D5.ld + */ + +MEMORY +{ + /* Infinity blootloader uses 4KB */ + FLASH (rx) : ORIGIN = 4K, LENGTH = 128K - 4K + RAM (rwx) : ORIGIN = 0x1FFFE0F8, LENGTH = 16K - 0xF8 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * _reset_init : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + __vector_table = .; + KEEP(*(.isr_vector)) + *(.text.Reset_Handler) + *(.text.System_Init) + . = ALIGN(4); + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + __bss_start__ = .; + *(.bss*) + *(COMMON) + __bss_end__ = .; + } > RAM + + .heap : + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy : + { + *(.stack) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/keyboard/infinity/mbed-infinity/system_MK20D5.c b/keyboard/infinity/mbed-infinity/system_MK20D5.c new file mode 100644 index 000000000..4f4e2a262 --- /dev/null +++ b/keyboard/infinity/mbed-infinity/system_MK20D5.c @@ -0,0 +1,299 @@ +/* +** ################################################################### +** Compilers: ARM Compiler +** Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manuals: K20P64M50SF0RM Rev. 1, Oct 2011 +** K20P32M50SF0RM Rev. 1, Oct 2011 +** K20P48M50SF0RM Rev. 1, Oct 2011 +** +** Version: rev. 1.0, 2011-12-15 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright: 2011 Freescale Semiconductor, Inc. All Rights Reserved. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2011-12-15) +** Initial version +** +** ################################################################### +*/ + +/** + * @file MK20D5 + * @version 1.0 + * @date 2011-12-15 + * @brief Device specific configuration file for MK20D5 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "MK20D5.h" + +#define DISABLE_WDOG 1 + +#define CLOCK_SETUP 3 +/* Predefined clock setups + 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode + Reference clock source for MCG module is the slow internal clock source 32.768kHz + Core clock = 41.94MHz, BusClock = 41.94MHz + 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode + Reference clock source for MCG module is an external crystal 8MHz + Core clock = 48MHz, BusClock = 48MHz + 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode + Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication + Core clock = 8MHz, BusClock = 8MHz +*/ + +/*---------------------------------------------------------------------------- + Define clock source values + *----------------------------------------------------------------------------*/ +#if (CLOCK_SETUP == 0) + #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */ + #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ + #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ + #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ + #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */ +#elif (CLOCK_SETUP == 1) + #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */ + #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ + #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ + #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ + #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */ +#elif (CLOCK_SETUP == 2) + #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */ + #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ + #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ + #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ + #define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */ +#elif (CLOCK_SETUP == 3) + /* for Infinity */ + #define CPU_XTAL_CLK_HZ 8000000u + #define CPU_XTAL32k_CLK_HZ 32768u + #define CPU_INT_SLOW_CLK_HZ 32768u + #define CPU_INT_FAST_CLK_HZ 4000000u + #define DEFAULT_SYSTEM_CLOCK 48000000u +#endif + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +void SystemInit (void) { +#if (DISABLE_WDOG) + /* Disable the WDOG module */ + /* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */ + WDOG->UNLOCK = (uint16_t)0xC520u; /* Key 1 */ + /* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */ + WDOG->UNLOCK = (uint16_t)0xD928u; /* Key 2 */ + /* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */ + WDOG->STCTRLH = (uint16_t)0x01D2u; +#endif /* (DISABLE_WDOG) */ +#if (CLOCK_SETUP == 0) + /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ + SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */ + /* Switch to FEI Mode */ + /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */ + MCG->C1 = (uint8_t)0x06u; + /* MCG->C2: ??=0,??=0,RANGE0=0,HGO=0,EREFS=0,LP=0,IRCS=0 */ + MCG->C2 = (uint8_t)0x00u; + /* MCG_C4: DMX32=0,DRST_DRS=1 */ + MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0u) | (uint8_t)0x20u); + /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */ + MCG->C5 = (uint8_t)0x00u; + /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */ + MCG->C6 = (uint8_t)0x00u; + while((MCG->S & MCG_S_IREFST_MASK) == 0u) { /* Check that the source of the FLL reference clock is the internal reference clock. */ + } + while((MCG->S & 0x0Cu) != 0x00u) { /* Wait until output of the FLL is selected */ + } +#elif (CLOCK_SETUP == 1) + /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ + SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */ + /* Switch to FBE Mode */ + /* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ + OSC0->CR = (uint8_t)0x00u; + /* MCG->C7: OSCSEL=0 */ + MCG->C7 = (uint8_t)0x00u; + /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ + MCG->C2 = (uint8_t)0x24u; + /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ + MCG->C1 = (uint8_t)0x9Au; + /* MCG->C4: DMX32=0,DRST_DRS=0 */ + MCG->C4 &= (uint8_t)~(uint8_t)0xE0u; + /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */ + MCG->C5 = (uint8_t)0x03u; + /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */ + MCG->C6 = (uint8_t)0x00u; + while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */ + } +#if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */ + while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */ + } +#endif + while((MCG->S & 0x0Cu) != 0x08u) { /* Wait until external reference clock is selected as MCG output */ + } + /* Switch to PBE Mode */ + /* MCG_C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */ + MCG->C5 = (uint8_t)0x03u; + /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=0 */ + MCG->C6 = (uint8_t)0x40u; + while((MCG->S & MCG_S_PLLST_MASK) == 0u) { /* Wait until the source of the PLLS clock has switched to the PLL */ + } + while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */ + } + /* Switch to PEE Mode */ + /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ + MCG->C1 = (uint8_t)0x1Au; + while((MCG->S & 0x0Cu) != 0x0Cu) { /* Wait until output of the PLL is selected */ + } + while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */ + } +#elif (CLOCK_SETUP == 2) + /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ + SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */ + /* Switch to FBE Mode */ + /* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ + OSC0->CR = (uint8_t)0x00u; + /* MCG->C7: OSCSEL=0 */ + MCG->C7 = (uint8_t)0x00u; + /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ + MCG->C2 = (uint8_t)0x24u; + /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ + MCG->C1 = (uint8_t)0x9Au; + /* MCG->C4: DMX32=0,DRST_DRS=0 */ + MCG->C4 &= (uint8_t)~(uint8_t)0xE0u; + /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */ + MCG->C5 = (uint8_t)0x00u; + /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */ + MCG->C6 = (uint8_t)0x00u; + while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */ + } +#if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */ + while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */ + } +#endif + while((MCG->S & 0x0CU) != 0x08u) { /* Wait until external reference clock is selected as MCG output */ + } + /* Switch to BLPE Mode */ + /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ + MCG->C2 = (uint8_t)0x24u; + +#elif (CLOCK_SETUP == 3) + /* for Infinity FEI: 48MHz */ + + /* OUTDIV1(core/system): 48/1, OUTDIV2(bus): 48/1, OUTDIV4(flash): 48/2 */ + SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) | SIM_CLKDIV1_OUTDIV4(1); + MCG->C1 = MCG_C1_IREFS_MASK | MCG_C1_IRCLKEN_MASK; + /* 32.768KHz x FLL(1464) = 48MHz */ + MCG->C4 = MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(1); + /* USB clock source: MCGPLLCLK/MCGFLLCLK */ + //SIM->SOPT2 = SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_TRACECLKSEL_MASK; + + while((MCG->S & MCG_S_IREFST_MASK) == 0u) { } + while((MCG->S & 0x0Cu) != 0x00u) { } +#endif +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { + uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */ + uint8_t Divider; + + if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) { + /* Output of FLL or PLL is selected */ + if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { + /* FLL is selected */ + if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) { + /* External reference clock is selected */ + if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) { + MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ + } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ + MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ + } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ + Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); + MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ + if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) { + MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */ + } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */ + } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */ + MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */ + } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */ + /* Select correct multiplier to calculate the MCG output clock */ + switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { + case 0x0u: + MCGOUTClock *= 640u; + break; + case 0x20u: + MCGOUTClock *= 1280u; + break; + case 0x40u: + MCGOUTClock *= 1920u; + break; + case 0x60u: + MCGOUTClock *= 2560u; + break; + case 0x80u: + MCGOUTClock *= 732u; + break; + case 0xA0u: + MCGOUTClock *= 1464u; + break; + case 0xC0u: + MCGOUTClock *= 2197u; + break; + case 0xE0u: + MCGOUTClock *= 2929u; + break; + default: + break; + } + } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */ + /* PLL is selected */ + Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK)); + MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ + Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u); + MCGOUTClock *= Divider; /* Calculate the MCG output clock */ + } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */ + } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) { + /* Internal reference clock is selected */ + if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) { + MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */ + } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */ + MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */ + } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */ + } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) { + /* External reference clock is selected */ + if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) { + MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ + } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ + MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ + } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ + } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */ + /* Reserved value */ + return; + } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */ + SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT))); +} diff --git a/keyboard/infinity/openocd.cfg b/keyboard/infinity/openocd.cfg deleted file mode 100644 index 2b0a63b93..000000000 --- a/keyboard/infinity/openocd.cfg +++ /dev/null @@ -1,13 +0,0 @@ -# mchack openocd -# https://github.com/mchck/mchck/wiki/Openocd -# -# adapter: frdm-kl05z with cmsis-dap firmware -# inteface: cmsis-dap -# transport: hla_swd -# target: MK20DX128VLF5 Freescale Kinetis - -# adapter/interface -source [find interface/cmsis-dap.cfg] - -# CPU -source [find k20dx32_flash.cfg] diff --git a/keyboard/infinity/tool/k20dx32_flash.cfg b/keyboard/infinity/tool/k20dx32_flash.cfg new file mode 100644 index 000000000..714d9991f --- /dev/null +++ b/keyboard/infinity/tool/k20dx32_flash.cfg @@ -0,0 +1,124 @@ +# FreeScale Kinetis K20 devices with 32kB Flash and 8kB Local On-Chip SRAM, +# Nemuisan's Special for MK20DN32VFT5,MK20DX32VFT5,MK10DN32VFT5,MK10DX32VFT5 + + +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME k20 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + if { [using_jtag] } { + set _CPUTAPID 0x4BA00477 + } { + # this is the SW-DP tap id not the jtag tap id + set _CPUTAPID 0x2BA01477 + } +} + +# Work-area is a space in RAM used for flash programming +# By default use 8kB +if { [info exists WORKAREASIZE] == 0 } { + set _WORKAREASIZE 0x2000 +} + +# Select "srst_only", Nemuisan said so! +echo "Kinetis MUST need Hardware SRST Control to Recover Secure-State!" +adapter_nsrst_delay 200 +reset_config srst_only + +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME + +# It is important that "kinetis mdm check_security" is called for +# 'examine-end' event and not 'eximine-start'. Calling it in 'examine-start' +# causes "kinetis mdm check_security" to fail the first time openocd +# calls it when it tries to connect after the CPU has been power-cycled. +$_CHIPNAME.cpu configure -event examine-end { + kinetis mdm check_security +# Uncomment when gone into s*ck'n secured state! +# kinetis mdm mass_erase +} + +# K20 has minimun 8kB of SRAM and starts at 1FFFF000. +$_TARGETNAME configure -work-area-phys 0x1FFFF000 -work-area-size $_WORKAREASIZE -work-area-backup 0 -rtos auto + +# MK20DN32VFT5,MK20DX32VFT5,MK10DN32VFT5,MK10DX32VFT5 has 32kB of flash memory. +flash bank $_CHIPNAME.pflash kinetis 0x00000000 0x8000 0 4 $_TARGETNAME + + +proc mt_flash {IMGFILE} { + flash write_image erase $IMGFILE + reset run + halt + verify_image $IMGFILE + reset run + shutdown +} + +proc mt_flash_bin {IMGFILE OFFSET} { + flash write_image erase $IMGFILE $OFFSET bin + reset run + halt + verify_image $IMGFILE $OFFSET bin + reset run + shutdown +} + +proc mt_flash_hex {IMGFILE} { + flash write_image erase $IMGFILE 0 ihex + reset run + halt + verify_image $IMGFILE 0 ihex + reset run + shutdown +} + +proc mt_flash_srec {IMGFILE} { + flash write_image erase $IMGFILE 0 s19 + reset run + halt + verify_image $IMGFILE 0 s19 + reset run + shutdown +} + +proc mass_erase {} { + kinetis mdm mass_erase +} + +proc eraser {} { +# Verbose procedure confirmed erase routine + flash info 0 +# CAUTION! "flash erase_sector 0 0 last" goes into secure state!!! +# USE "mass_erase" command instead of +# flash erase_sector 0 0 last + mass_erase + shutdown +} + + +#debug_level 3 +# HLA doesn't have cortex_m commands +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} +adapter_khz 1000 +reset_config srst_only srst_nogate connect_assert_srst +gdb_target_description disable +init +reset init diff --git a/keyboard/infinity/tool/openocd.cfg b/keyboard/infinity/tool/openocd.cfg new file mode 100644 index 000000000..2b0a63b93 --- /dev/null +++ b/keyboard/infinity/tool/openocd.cfg @@ -0,0 +1,13 @@ +# mchack openocd +# https://github.com/mchck/mchck/wiki/Openocd +# +# adapter: frdm-kl05z with cmsis-dap firmware +# inteface: cmsis-dap +# transport: hla_swd +# target: MK20DX128VLF5 Freescale Kinetis + +# adapter/interface +source [find interface/cmsis-dap.cfg] + +# CPU +source [find k20dx32_flash.cfg] -- cgit v1.2.3-24-g4f1b